FLAIRS: FPGA-Accelerated Inference-Resistant & Secure Federated Learning

TL;DR

This paper introduces FPGA-accelerated techniques to enhance the security and efficiency of federated learning, effectively defending against backdoor and inference attacks while significantly improving performance.

Contribution

It presents a novel FPGA-based framework that mitigates inference and backdoor attacks in federated learning, overcoming performance limitations of existing software solutions.

Findings

300x speed-up on IoT-Traffic dataset

506x speed-up on CIFAR-10 dataset

Effective defense against inference and backdoor attacks

Abstract

Federated Learning (FL) has become very popular since it enables clients to train a joint model collaboratively without sharing their private data. However, FL has been shown to be susceptible to backdoor and inference attacks. While in the former, the adversary injects manipulated updates into the aggregation process; the latter leverages clients' local models to deduce their private data. Contemporary solutions to address the security concerns of FL are either impractical for real-world deployment due to high-performance overheads or are tailored towards addressing specific threats, for instance, privacy-preserving aggregation or backdoor defenses. Given these limitations, our research delves into the advantages of harnessing the FPGA-based computing paradigm to overcome performance bottlenecks of software-only solutions while mitigating backdoor and inference attacks. We utilize FPGA-based enclaves to address inference attacks during the aggregation process of FL. We adopt an advanced backdoor-aware aggregation algorithm on the FPGA to counter backdoor attacks. We implemented and evaluated our method on Xilinx VMK-180, yielding a significant speed-up of around 300 times on the IoT-Traffic dataset and more than 506 times on the CIFAR-10 dataset.