CMOS on-chip thermometry at deep cryogenic temperatures

TL;DR

This paper presents four CMOS-compatible on-chip thermometry methods suitable for deep cryogenic temperatures, crucial for quantum computing and cryogenic electronics, demonstrating their sensitivity and integration potential.

Contribution

The paper introduces four novel CMOS-compatible thermometry techniques for deep cryogenic temperatures, including superconductivity and Coulomb blockade-based methods.

Findings

Methods cover temperature range from milliKelvin to room temperature.

Sensitivity benchmarks show effective detection of local heating.

Demonstrated integration with CMOS chips for cryogenic applications.

Abstract

Accurate on-chip temperature sensing is critical for the optimal performance of modern CMOS integrated circuits (ICs), to understand and monitor localized heating around the chip during operation. The development of quantum computers has stimulated much interest in ICs operating a deep cryogenic temperatures (typically 0.01 - 4 K), in which the reduced thermal conductivity of silicon and silicon oxide, and the limited cooling power budgets make local on-chip temperature sensing even more important. Here, we report four different methods for on-chip temperature measurements native to complementary metal-oxide-semiconductor (CMOS) industrial fabrication processes. These include secondary and primary thermometry methods and cover conventional thermometry structures used at room temperature as well as methods exploiting phenomena which emerge at cryogenic temperatures, such as superconductivity and Coulomb blockade. We benchmark the sensitivity of the methods as a function of temperature and use them to measure local excess temperature produced by on-chip heating elements. Our results demonstrate thermometry methods that may be readily integrated in CMOS chips with operation from the milliKelivin range to room temperature.