PATRONoC: Parallel AXI Transport Reducing Overhead for Networks-on-Chip targeting Multi-Accelerator DNN Platforms at the Edge
Vikram Jain, Matheus Cavalcante, Nazareno Bruschi, Michael Rogenmoser,, Thomas Benz, Andreas Kurth, Davide Rossi, Luca Benini, Marian Verhelst

TL;DR
PATRONoC is an open-source, AXI-compliant NoC fabric designed for multi-core DNN platforms, significantly reducing overhead and increasing throughput and area efficiency compared to classical NoCs.
Contribution
It introduces PATRONoC, a novel parallel AXI-based NoC architecture optimized for DNN workloads, with improved efficiency and throughput over existing solutions.
Findings
34% higher area efficiency at 1 GHz
2-8X throughput improvement over baseline
up to 350 GiB/s throughput on workloads
Abstract
Emerging deep neural network (DNN) applications require high-performance multi-core hardware acceleration with large data bursts. Classical network-on-chips (NoCs) use serial packet-based protocols suffering from significant protocol translation overheads towards the endpoints. This paper proposes PATRONoC, an open-source fully AXI-compliant NoC fabric to better address the specific needs of multi-core DNN computing platforms. Evaluation of PATRONoC in a 2D-mesh topology shows 34% higher area efficiency compared to a state-of-the-art classical NoC at 1 GHz. PATRONoC's throughput outperforms a baseline NoC by 2-8X on uniform random traffic and provides a high aggregated throughput of up to 350 GiB/s on synthetic and DNN workload traffic.
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