MoS$_{2}$/Al$_{0.68}$Sc$_{0.32}$N negative capacitance field-effect transistors

TL;DR

This paper demonstrates a MoS2 negative capacitance FET using AlScN ferroelectric material, achieving reduced hysteresis and subthreshold swing below thermionic limits, with potential for low-power logic applications.

Contribution

It reports the first MoS2 NC-FET with AlScN ferroelectric, showing minimized hysteresis and sub-60 mV/dec subthreshold swing through dielectric layer engineering.

Findings

Hysteresis minimized with dielectric layer matching capacitance.

Subthreshold swing below thermionic limit (~36-60 mV/dec).

Consistent threshold voltages across large-area MoS2 arrays.

Abstract

Al$_{0.68}$Sc$_{0.32}$N (AlScN) has gained attention for its outstanding ferroelectric properties, including a high coercive field and high remnant polarization. Although AlScN-based ferroelectric field-effect transistors (FETs) for memory applications have been demonstrated, a device for logic applications with minimal hysteresis has not been reported. This study reports on the transport characteristics of a MoS$_{2}$ negative capacitance FET (NCFET) based on an AlScN ferroelectric material. We experimentally demonstrate the effect of a dielectric layer in the gate stack on the memory window and subthreshold swing (SS) of the NCFET. We show that the hysteresis behavior of transfer characteristics in the NCFET can be minimized with the inclusion of a non-ferroelectric dielectric layer, which fulfills the capacitance-matching condition. Remarkably, we also observe the NC effect in MoS$_{2}$/AlScN NCFETs arrays based on large-area monolayer MoS$_{2}$ synthesized by chemical vapor deposition, showing the SS values smaller than its thermionic limit (~36-60 mV/dec) and minimal variation in threshold voltages (< 20 mV).