Implementation of Fast and Power Efficient SEC-DAEC and SEC-DAEC-TAEC Codecs on FPGA

TL;DR

This paper presents FPGA implementations of fast, low-power SEC-DAEC and SEC-DAEC-TAEC codecs with various data lengths, improving error correction for memory devices affected by radiation-induced soft errors.

Contribution

It introduces optimized FPGA implementations of SEC-DAEC and SEC-DAEC-TAEC codecs with reduced delay and power consumption, suitable for protecting memories against multi-bit adjacent errors.

Findings

Comparable area to existing designs

Reduced delay in FPGA implementation

Lower power consumption achieved

Abstract

The reliability of memory devices is affected by radiation induced soft errors. Multiple cell upsets (MCUs) caused by radiation corrupt data stored in multiple cells within memories. Error correction codes (ECCs) are typically used to mitigate the effects of MCUs. Single error correction-double error detection (SEC-DED) codes are not the right choice against MCUs, but are more suitable for protecting memory against single cell upset (SCU). Single error correction-double adjacent error correction (SEC-DAEC) and single error correction-double adjacent error correction-triple adjacent error correction (SEC-DAEC-TAEC) codes are more suitable due to the increasing tendency of adjacent errors. This paper presents the implementation of fast and low power multi-bit adjacent error correction codes for protecting memories. Related SEC-DAEC and SEC-DAEC-TAEC codecs with data length of 16-bit, 32-bit and 64-bit have been implemented. It is found from FPGA based implementation results that the modified designs have comparable area and have less delay and power consumption.