SPICE Modeling of Memcomputing Logic Gates

TL;DR

This paper introduces SPICE models for memcomputing logic gates, demonstrating their behavior and correcting previous inconsistencies, thereby making memcomputing more accessible for hardware implementation.

Contribution

It provides the first detailed SPICE models of memcomputing gates and corrects prior schematic inaccuracies, facilitating hardware deployment.

Findings

Successful simulation of single memcomputing gates

Demonstration of small self-organizing circuits

Correction of schematic inconsistencies in literature

Abstract

Memcomputing logic gates generalize the traditional Boolean logic gates for operation in the reverse direction. According to the literature, this functionality enables the efficient solution of computationally-intensive problems including factorization and NP-complete problems. To approach the deployment of memcomputing gates in hardware, this paper introduces SPICE models of memcomputing logic gates following their original definition. Using these models, we demonstrate the behavior of single gates as well as small self-organizing circuits. We also correct some inconsistencies in the prior literature. Importantly, the correct schematics of dynamic correction module is reported here for the first time. Our work makes memcomputing more accessible to those who are interested in this emerging computing technology.