High-definition event frame generation using SoC FPGA devices

TL;DR

This paper demonstrates the feasibility of generating high-definition event frames on FPGA devices, enabling advanced vision tasks like object detection with resource-efficient implementations.

Contribution

It presents a hardware implementation approach for high-resolution event data processing on FPGA, comparing resource requirements and showcasing practical applications.

Findings

Feasibility of high-definition event frame generation on FPGA

Comparison of hardware resource requirements for different data representations

Potential for using generated frames in vision algorithms like object detection

Abstract

In this paper we have addressed the implementation of the accumulation and projection of high-resolution event data stream (HD -1280 x 720 pixels) onto the image plane in FPGA devices. The results confirm the feasibility of this approach, but there are a number of challenges, limitations and trade-offs to be considered. The required hardware resources of selected data representations, such as binary frame, event frame, exponentially decaying time surface and event frequency, were compared with those available on several popular platforms from AMD Xilinx. The resulting event frames can be used for typical vision algorithms, such as object classification and detection, using both classical and deep neural network methods.