FPGA Implementation of Robust Residual Generator

TL;DR

This paper details the implementation of a robust residual generator on FPGA, focusing on digital domain processing, model development, and parameter selection for improved detection performance.

Contribution

It introduces a method for implementing a robust residual generator on FPGA, including model development and parameter optimization in digital domain.

Findings

Successful FPGA implementation of residual generator

Enhanced detection robustness through parameter tuning

Demonstrated digital domain processing advantages

Abstract

In this paper, one can explicitly see the process of implementing the robust residual generator on digital domain, especially on FPGA. Firstly, the baseline model is developed in double precision floating point format. To develop the baseline model, key parameters such as SNR and detection window length are selected in the identification stage. (Please refer to the uploaded paper because this box doesn't accept more typing beyond this point)