Envisioning a Safety Island to Enable HPC Devices in Safety-Critical Domains

TL;DR

This paper proposes a versatile, open-source safety island concept based on RISC-V to enhance safety features for HPC devices in safety-critical autonomous systems, aiming for broad applicability and ease of adoption.

Contribution

It introduces a novel safety island design with comprehensive safety features, implemented with open source RISC-V components to facilitate adoption in safety-critical HPC applications.

Findings

Designed a safety island with broad safety features

Utilized open source RISC-V components for implementation

Potential applications extend beyond safety domains

Abstract

HPC (High Performance Computing) devices increasingly become the only alternative to deliver the performance needed in safety-critical autonomous systems (e.g., autonomous cars, unmanned planes) due to deploying large and powerful multicores along with accelerators such as GPUs. However, the support that those HPC devices offer to realize safety-critical systems on top is heterogeneous. Safety islands have been devised to be coupled to HPC devices and complement them to meet the safety requirements of an increased set of applications, yet the variety of concepts and realizations is large. This paper presents our own concept of a safety island with two goals in mind: (1) offering a wide set of features to enable the broadest set of safety applications for each HPC device, and (2) being realized with open source components based on RISC-V ISA to ease its use and adoption. In particular, we present our safety island concept, the key features we foresee it should include, and its potential application beyond safety.