Probabilistic Compute-in-Memory Design For Efficient Markov Chain Monte Carlo Sampling
Yihan Fu, Daijing Shi, Anjunyi Fan, Wenshuo Yue, Yuchao Yang, Ru, Huang, Bonan Yan

TL;DR
This paper introduces a novel compute-in-memory hardware design for Markov Chain Monte Carlo sampling, significantly improving energy efficiency and throughput by leveraging SRAM stochasticity, a pseudo-read operation, and new random number generation circuits.
Contribution
It proposes a new CIM-based MCMC architecture with innovative random number generation and data copying methods, achieving high efficiency and throughput improvements.
Findings
Energy efficiency of 0.53 pJ/sample
High throughput of 166.7 million samples per second
Energy efficiency improved by over 10^11 times compared to conventional processors
Abstract
Markov chain Monte Carlo (MCMC) is a widely used sampling method in modern artificial intelligence and probabilistic computing systems. It involves repetitive random number generations and thus often dominates the latency of probabilistic model computing. Hence, we propose a compute-in-memory (CIM) based MCMC design as a hardware acceleration solution. This work investigates SRAM bitcell stochasticity and proposes a novel ``pseudo-read'' operation, based on which we offer a block-wise random number generation circuit scheme for fast random number generation. Moreover, this work proposes a novel multi-stage exclusive-OR gate (MSXOR) design method to generate strictly uniformly distributed random numbers. The probability error deviating from a uniform distribution is suppressed under . Also, this work presents a novel in-memory copy circuit scheme to realize data copy inside a…
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Taxonomy
TopicsAdvanced Memory and Neural Computing · Parallel Computing and Optimization Techniques · Low-power high-performance VLSI design
