Constructive plaquette compilation for the parity architecture

TL;DR

This paper introduces a constructive algorithm for parity compilation using plaquettes, enabling efficient layout and implementation of higher-order optimization problems in quantum architectures.

Contribution

It presents the first constructive, plaquette-based parity compilation algorithm for arbitrary higher-order problems, supporting adiabatic and digital quantum protocols.

Findings

Enables native plaquette layout for parity mapping

Supports parallelized digital circuit implementation

Optimizes ancilla qubit usage

Abstract

Parity compilation is the challenge of laying out the required constraints for the parity mapping in a local way. We present the first constructive compilation algorithm for the parity architecture using plaquettes for arbitrary higher-order optimization problems. This enables adiabatic protocols, where the plaquette layout can natively be implemented, as well as fully parallelized digital circuits. The algorithm builds a rectangular layout of plaquettes, where in each layer of the rectangle at least one constraint is added. The core idea is that each constraint, consisting of any qubits on the boundary of the rectangle and some new qubits, can be decomposed into plaquettes with a deterministic procedure using ancillas. We show how to pick a valid set of constraints and how this decomposition works. We further give ways to optimize the ancilla count and show how to implement optimization problems with additional constraints.