Impact of gate-level clustering on automated system partitioning of 3D-ICs

TL;DR

This paper investigates how different gate clustering methods affect the partitioning and performance of 3D integrated circuits, showing that tailored clustering improves wire-length, power, and frequency metrics.

Contribution

It demonstrates that the choice of clustering method significantly impacts 3D-IC partitioning outcomes, emphasizing the need for design-specific approaches.

Findings

Wire-length savings of up to 31%

Total power reduction of up to 22%

Frequency improvements of up to 15%

Abstract

When partitioning gate-level netlists using graphs, it is beneficial to cluster gates to reduce the order of the graph and preserve some characteristics of the circuit that the partitioning might degrade. Gate clustering is even more important for netlist partitioning targeting 3D system integration. In this paper, we make the argument that the choice of clustering method for 3D-ICs partitioning is not trivial and deserves careful consideration. To support our claim, we implemented three clustering methods that were used prior to partitioning two synthetic designs representing two extremes of the circuits medium/long interconnect diversity spectrum. Automatically partitioned netlists are then placed and routed in 3D to compare the impact of clustering methods on several metrics. From our experiments, we see that the clustering method indeed has a different impact depending on the design considered and that a circuit-blind, universal partitioning method is not the way to go, with wire-length savings of up to 31%, total power of up to 22%, and effective frequency of up to 15% compared to other methods. Furthermore, we highlight that 3D-ICs open new opportunities to design systems with a denser interconnect, drastically reducing the design utilization of circuits that would not be considered viable in 2D.