Enhancing Data Storage Reliability and Error Correction in Multilevel NOR and NAND Flash Memories through Optimal Design of BCH Codes

TL;DR

This paper presents an optimized BCH decoder design with parallel architecture and XOR sharing algorithms to improve error correction speed and reduce hardware overhead in flash memory storage.

Contribution

It introduces a novel BCH decoder architecture with parallel processing and XOR sharing to enhance speed and hardware efficiency in flash memory error correction.

Findings

Error correction time is significantly reduced.

Hardware overhead of BCH decoder is decreased.

Simulation confirms improved performance over existing methods.

Abstract

The size reduction of transistors in the latest flash memory generation has resulted in programming and data erasure issues within these designs. Consequently, ensuring reliable data storage has become a significant challenge for these memory structures. To tackle this challenge, error-correcting codes like BCH (Bose-Chaudhuri-Hocquenghem) codes are employed in the controllers of these memories. When decoding BCH codes, two crucial factors are the delay in error correction and the hardware requirements of each sub-block. This article proposes an effective solution to enhance error correction speed and optimize the decoder circuit's efficiency. It suggests implementing a parallel architecture for the BCH decoder's sub-blocks and utilizing pipeline techniques. Moreover, to reduce the hardware requirements of the BCH decoder block, an algorithm based on XOR sharing is introduced to eliminate redundant gates in the search Chien block. The proposed decoder is simulated using the VHDL hardware description language and subsequently synthesized with Xilinx ISE software. Simulation results indicate that the proposed algorithm not only significantly reduces error correction time but also achieves a noticeable reduction in the hardware overhead of the BCH decoder block compared to similar methods.