Non-Ideal Program-Time Conservation in Charge Trap Flash for Deep Learning

TL;DR

This paper investigates the non-ideal charge accumulation effects in Charge Trap Flash memory used for in-memory deep learning accelerators, revealing how pulse parameters influence threshold voltage shifts and system performance.

Contribution

It experimentally characterizes non-ideal program-time conservation in CTF devices and explains the underlying mechanisms affecting in-memory computing accuracy.

Findings

Shorter pulses (<2μs) cause abrupt V_T shift drops

Fragmenting total ON-time reduces cumulative V_T shift

V_T shift depends on pulse gap and recovers with smaller gaps

Abstract

Training deep neural networks (DNNs) is computationally intensive but arrays of non-volatile memories like Charge Trap Flash (CTF) can accelerate DNN operations using in-memory computing. Specifically, the Resistive Processing Unit (RPU) architecture uses the voltage-threshold program by stochastic encoded pulse trains and analog memory features to accelerate vector-vector outer product and weight update for the gradient descent algorithms. Although CTF, offering high precision, has been regarded as an excellent choice for implementing RPU, the accumulation of charge due to the applied stochastic pulse trains is ultimately of critical significance in determining the final weight update. In this paper, we report the non-ideal program-time conservation in CTF through pulsing input measurements. We experimentally measure the effect of pulse width and pulse gap, keeping the total ON-time of the input pulse train constant, and report three non-idealities: (1) Cumulative V_T shift reduces when total ON-time is fragmented into a larger number of shorter pulses, (2) Cumulative V_T shift drops abruptly for pulse widths < 2 {\mu}s, (3) Cumulative V_T shift depends on the gap between consecutive pulses and the V_T shift reduction gets recovered for smaller gaps. We present an explanation based on a transient tunneling field enhancement due to blocking oxide trap-charge dynamics to explain these non-idealities. Identifying and modeling the responsible mechanisms and predicting their system-level effects during learning is critical. This non-ideal accumulation is expected to affect algorithms and architectures relying on devices for implementing mathematically equivalent functions for in-memory computing-based acceleration.