A 137.5 TOPS/W SRAM Compute-in-Memory Macro with 9-b Memory Cell-Embedded ADCs and Signal Margin Enhancement Techniques for AI Edge Applications

TL;DR

This paper introduces a high-precision SRAM-based compute-in-memory macro with embedded ADCs and margin enhancement techniques, achieving 137.5 TOPS/W for AI edge applications by enabling efficient 4x4-bit MAC operations with high linearity and accuracy.

Contribution

It presents a novel SRAM macro with integrated ADCs and margin enhancement methods, improving energy efficiency, area, and computation accuracy for AI edge computing.

Findings

Achieves 137.5 TOPS/W energy efficiency.

Supports 4x4-bit MAC operations with 9-bit output.

Enhances accuracy with MAC-folding and boosted-clipping techniques.

Abstract

In this paper, we propose a high-precision SRAM-based CIM macro that can perform 4x4-bit MAC operations and yield 9-bit signed output. The inherent discharge branches of SRAM cells are utilized to apply time-modulated MAC and 9-bit ADC readout operations on two bit-line capacitors. The same principle is used for both MAC and A-to-D conversion ensuring high linearity and thus supporting large number of analog MAC accumulations. The memory cell-embedded ADC eliminates the use of separate ADCs and enhances energy and area efficiency. Additionally, two signal margin enhancement techniques, namely the MAC-folding and boosted-clipping schemes, are proposed to further improve the CIM computation accuracy.