Designing Secure Interconnects for Modern Microelectronics: From SoCs to Emerging Chiplet-Based Architectures

TL;DR

This paper addresses security vulnerabilities in modern microelectronics interconnects, extending obfuscation and encryption techniques to chiplet architectures to protect against reverse engineering and IP theft with minimal performance impact.

Contribution

It extends existing NoC security methods to chiplet-based systems, introducing new obfuscation, authentication, and encryption strategies for intra- and inter-chiplet communication.

Findings

Effective security enhancements for chiplet interconnects.

Minimal performance overhead demonstrated.

Practical solutions for high-security applications.

Abstract

The globalization of semiconductor supply chains has exposed Network-on-Chip (NoC) interconnects in System-on-Chip (SoC) architectures to critical security risks, including reverse engineering and IP theft. To address these threats, this work builds on two methodologies: ObNoCs [11], which obfuscates NoC topologies using programmable multiplexers, and POTENT [10], which enhances post-synthesis security against SAT-based attacks. These techniques ensure robust protection of NoC interconnects with minimal performance overhead. As the industry shifts to chiplet-based heterogeneous architectures, this research extends ObNoCs and POTENT to secure intra- and inter-chiplet interconnects. New challenges, such as safeguarding inter-chiplet communication and interposer design, are addressed through enhanced obfuscation, authentication, and encryption mechanisms. Experimental results demonstrate the practicality of these approaches for high-security applications, ensuring trust and reliability in monolithic and modular systems.