Large-scale on-chip integration of gate-voltage addressable hybrid superconductor-semiconductor quantum wells field effect nano-switch arrays

TL;DR

This paper demonstrates large-scale, gate-controlled hybrid superconductor-semiconductor quantum chip arrays with 144 junctions, enabling scalable, addressable quantum devices for cryogenic nanoelectronics and quantum computing applications.

Contribution

It introduces a novel scalable chip architecture with integrated hybrid junctions controlled by split gates, advancing the development of large quantum circuits.

Findings

Successful fabrication of 18 quantum chips with 144 hybrid junctions

Demonstrated control over junction conductance states at cryogenic temperatures

Achieved reproducible switching and high quantum yield in the devices

Abstract

Stable, reproducible, scalable, addressable, and controllable hybrid superconductor-semiconductor (S-Sm) junctions and switches are key circuit elements and building blocks of gate-based quantum processors. The electrostatic field effect produced by the split gate voltages facilitates the realisation of nano-switches that can control the conductance or current in the hybrid S-Sm circuits based on 2D semiconducting electron systems. Here, we experimentally demonstrate a novel realisation of large-scale scalable, and gate voltage controllable hybrid field effect quantum chips. Each chip contains arrays of split gate field effect hybrid junctions, that work as conductance switches, and are made from In0.75Ga0.25As quantum wells integrated with Nb superconducting electronic circuits. Each hybrid junction in the chip can be controlled and addressed through its corresponding source-drain and two global split gate contact pads that allow switching between their (super)conducting and insulating states. We fabricate a total of 18 quantum chips with 144 field effect hybrid Nb- In0.75Ga0.25As 2DEG-Nb quantum wires and investigate the electrical response, switching voltage (on/off) statistics, quantum yield, and reproducibility of several devices at cryogenic temperatures. The proposed integrated quantum device architecture allows control of individual junctions in a large array on a chip useful for the development of emerging cryogenic nanoelectronics circuits and systems for their potential applications in fault-tolerant quantum technologies.