Memory-Immersed Collaborative Digitization for Area-Efficient Compute-in-Memory Deep Learning
Shamma Nasrin, Maeesha Binte Hashem, Nastaran Darabi, Benjamin, Parpillon, Farah Fahim, Wilfred Gomes, and Amit Ranjan Trivedi

TL;DR
This paper introduces a memory-immersed collaborative digitization scheme for compute-in-memory deep learning that significantly reduces area and energy consumption of ADCs, enabling more arrays to be integrated for improved parallelism.
Contribution
It proposes a novel in-memory digitization approach using parasitic bit lines for area-efficient successive approximation ADCs in compute-in-memory architectures.
Findings
Achieves 25x less area and 1.4x less energy than a 40 nm 5-bit SAR ADC.
Replaces traditional ADCs with in-memory digitization to improve area and energy efficiency.
Demonstrated on a 65 nm CMOS test chip with significant improvements over conventional ADCs.
Abstract
This work discusses memory-immersed collaborative digitization among compute-in-memory (CiM) arrays to minimize the area overheads of a conventional analog-to-digital converter (ADC) for deep learning inference. Thereby, using the proposed scheme, significantly more CiM arrays can be accommodated within limited footprint designs to improve parallelism and minimize external memory accesses. Under the digitization scheme, CiM arrays exploit their parasitic bit lines to form a within-memory capacitive digital-to-analog converter (DAC) that facilitates area-efficient successive approximation (SA) digitization. CiM arrays collaborate where a proximal array digitizes the analog-domain product-sums when an array computes the scalar product of input and weights. We discuss various networking configurations among CiM arrays where Flash, SA, and their hybrid digitization steps can be efficiently…
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Taxonomy
TopicsAdvanced Memory and Neural Computing · Ferroelectric and Negative Capacitance Devices · Parallel Computing and Optimization Techniques
