Content Addressable Memories and Transformable Logic Circuits Based on Ferroelectric Reconfigurable Transistors for In-Memory Computing
Zijing Zhao, Junzhe Kang, Ashwin Tunga, Hojoon Ryu, Ankit Shukla,, Shaloo Rakheja, and Wenjuan Zhu

TL;DR
This paper introduces a novel ferroelectric reconfigurable transistor-based content addressable memory and logic circuits that enable high-density, low-power data processing with reconfigurable functions suitable for AI and machine learning.
Contribution
It presents a single-transistor CAM design and reconfigurable logic gates using ferroelectric transistors, improving area efficiency and enabling real-time reconfiguration.
Findings
Demonstrated 1-transistor-per-bit CAM with XOR/XNOR matching.
Achieved multi-bit matching and Hamming distance measurement.
Reconfigurable NAND/NOR logic gates with real-time transformation.
Abstract
As a promising alternative to the Von Neumann architecture, in-memory computing holds the promise of delivering high computing capacity while consuming low power. Content addressable memory (CAM) can implement pattern matching and distance measurement in memory with massive parallelism, making them highly desirable for data-intensive applications. In this paper, we propose and demonstrate a novel 1-transistor-per-bit CAM based on the ferroelectric reconfigurable transistor. By exploiting the switchable polarity of the ferroelectric reconfigurable transistor, XOR/XNOR-like matching operation in CAM can be realized in a single transistor. By eliminating the need for the complementary circuit, these non-volatile CAMs based on reconfigurable transistors can offer a significant improvement in area and energy efficiency compared to conventional CAMs. NAND- and NOR-arrays of CAMs are also…
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Taxonomy
TopicsAdvanced Memory and Neural Computing · Ferroelectric and Negative Capacitance Devices · Semiconductor materials and devices
