Securing Cloud FPGAs Against Power Side-Channel Attacks: A Case Study on Iterative AES
Nithyashankari Gummidipoondi Jayasankaran, Hao Guo, Satwik Patnaik,, Jeyavijayan (JV) Rajendran, and Jiang Hu

TL;DR
This paper investigates power side-channel attacks on cloud FPGA AES implementations, enhancing sensor sensitivity and proposing placement-based defenses to improve security in cloud environments.
Contribution
It introduces a placement-based defense strategy and improves sensor sensitivity, enabling effective key recovery with fewer traces in cloud FPGA AES security.
Findings
Enhanced TDC sensor sensitivity reduces traces needed for key disclosure.
Placement-based defense effectively mitigates power side-channel attacks.
AES with additional logic offers comparable or better security than existing methods.
Abstract
The various benefits of multi-tenanting, such as higher device utilization and increased profit margin, intrigue the cloud field-programmable gate array (FPGA) servers to include multi-tenanting in their infrastructure. However, this property makes these servers vulnerable to power side-channel (PSC) attacks. Logic designs such as ring oscillator (RO) and time-to-digital converter (TDC) are used to measure the power consumed by security critical circuits, such as advanced encryption standard (AES). Firstly, the existing works require higher minimum traces for disclosure (MTD). Hence, in this work, we improve the sensitivity of the TDC-based sensors by manually placing the FPGA primitives inferring these sensors. This enhancement helps to determine the 128-bit AES key using 3.8K traces. Secondly, the existing defenses use ROs to defend against PSC attacks. However, cloud servers such as…
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Taxonomy
TopicsCryptographic Implementations and Security · Physical Unclonable Functions (PUFs) and Hardware Security · Security and Verification in Computing
