Matrix Multiplication Using Only Addition

TL;DR

This paper proposes a novel approach to matrix multiplication that eliminates the need for multiplication circuits, potentially enabling faster and more energy-efficient hardware implementations for machine learning tasks.

Contribution

It introduces a method to perform matrix multiplication using only addition operations, removing the need for scalar multipliers in hardware design.

Findings

Potential for faster matrix multiplication hardware

Reduction in chip complexity and energy consumption

Enabling more processors on the same chip area

Abstract

Matrix multiplication consumes a large fraction of the time taken in many machine-learning algorithms. Thus, accelerator chips that perform matrix multiplication faster than conventional processors or even GPU's are of increasing interest. In this paper, we demonstrate a method of performing matrix multiplication without a scalar multiplier circuit. In many cases of practical interest, only a single addition and a single on-chip copy operation are needed to replace a multiplication. It thus becomes possible to design a matrix-multiplier chip that, because it does not need time, space- and energy-consuming multiplier circuits, can hold many more processors, and thus provide a net speedup.