Macro Placement by Wire-Mask-Guided Black-Box Optimization

TL;DR

This paper introduces WireMask-BBO, a black-box optimization framework for macro placement in chip design, achieving shorter wirelength and faster results compared to previous methods, and capable of improving existing placements significantly.

Contribution

The paper presents a novel wire-mask-guided black-box optimization framework for macro placement, enhancing efficiency and solution quality in chip floorplanning.

Findings

Achieves significantly shorter HPWL than previous methods.

Reduces optimization time compared to existing approaches.

Can improve existing placements by up to 50% in HPWL.

Abstract

The development of very large-scale integration (VLSI) technology has posed new challenges for electronic design automation (EDA) techniques in chip floorplanning. During this process, macro placement is an important subproblem, which tries to determine the positions of all macros with the aim of minimizing half-perimeter wirelength (HPWL) and avoiding overlapping. Previous methods include packing-based, analytical and reinforcement learning methods. In this paper, we propose a new black-box optimization (BBO) framework (called WireMask-BBO) for macro placement, by using a wire-mask-guided greedy procedure for objective evaluation. Equipped with different BBO algorithms, WireMask-BBO empirically achieves significant improvements over previous methods, i.e., achieves significantly shorter HPWL by using much less time. Furthermore, it can fine-tune existing placements by treating them as initial solutions, which can bring up to 50% improvement in HPWL. WireMask-BBO has the potential to significantly improve the quality and efficiency of chip floorplanning, which makes it appealing to researchers and practitioners in EDA and will also promote the application of BBO. Our code is available at https://github.com/lamda-bbo/WireMask-BBO.