Retrospective: RAIDR: Retention-Aware Intelligent DRAM Refresh

TL;DR

RAIDR introduces a low-cost, retention-aware DRAM refresh technique that significantly reduces energy consumption and performance overheads by exploiting variation in data retention times across DRAM rows, especially beneficial for future high-capacity DRAMs.

Contribution

The paper presents a novel, simple system-DRAM co-design approach that groups DRAM rows by retention time and applies different refresh rates, improving efficiency as DRAM capacity scales.

Findings

Significant performance improvement over traditional refresh methods

Energy savings achieved through retention-aware refresh scheduling

Benefits increase with larger DRAM chip capacities

Abstract

Dynamic Random Access Memory (DRAM) is the prevalent memory technology used to build main memory systems of almost all computers. A fundamental shortcoming of DRAM is the need to refresh memory cells to keep stored data intact. DRAM refresh consumes energy and degrades performance. It is also a technology scaling challenge as its negative effects become worse as DRAM cell size reduces and DRAM chip capacity increases. Our ISCA 2012 paper, RAIDR, examines the DRAM refresh problem from a modern computing systems perspective, demonstrating its projected impact on systems with higher-capacity DRAM chips expected to be manufactured in the future. It proposes and evaluates a simple and low-cost solution that greatly reduces the performance & energy overheads of refresh by exploiting variation in data retention times across DRAM rows. The key idea is to group the DRAM rows into bins in terms of their minimum data retention times, store the bins in low-cost Bloom filters, and refresh rows in different bins at different rates. Evaluations in our paper (and later works) show that the idea greatly improves performance & energy efficiency and its benefits increase with DRAM chip capacity. The paper embodies an approach we have termed system-DRAM co-design. This short retrospective provides a brief analysis of our RAIDR paper and its impact. We briefly describe the mindset and circumstances that led to our focus on the DRAM refresh problem and RAIDR's development, discuss later works that provided improved analyses and solutions, and make some educated guesses on what the future may bring on the DRAM refresh problem (and more generally in DRAM technology scaling).