Clean BN encapsulated 2D FETs with lithography compatible contacts

TL;DR

This paper demonstrates a method to integrate lithography-compatible contacts into BN-encapsulated 2D FETs, achieving high device quality and charge mobility comparable to more complex fabrication processes.

Contribution

It introduces a straightforward approach for integrating lithography-defined contacts into BN-encapsulated 2D FETs, maintaining high device quality and intrinsic charge transport properties.

Findings

Low hysteresis of ca. 2 mV in FETs

Interfacial charged impurity density of ca. 10^11 cm^-2

Charge mobilities over 1000 cm^2/V·s at low temperatures

Abstract

Device passivation through ultraclean hexagonal BN encapsulation is proven one of the most effective ways for constructing high-quality devices with atomically thin semiconductors that preserves the ultraclean interface quality and intrinsic charge transport behavior. However, it remains challenging to integrate lithography compatible contact electrodes with flexible distributions and patterns. Here, we report the feasibility in straightforwardly integrating lithography defined contacts into BN encapsulated 2D FETs, giving rise to overall device quality comparable to the state-of-the-art results from the painstaking pure dry transfer processing. Electronic characterization on FETs consisting of WSe$_2$ and MoS$_2$ channels reveals an extremely low scanning hysteresis of ca. 2 mV on average, a low density of interfacial charged impurity of ca. $10^{11}\,$cm$^{-2}$, and generally high charge mobilities over $1000\,$cm$^{2}\cdot$V$^{-1}\cdot$s$^{-1}$ at low temperatures. The overall high device qualities verify the viability in directly integrating lithography defined contacts into BN encapsulated devices to exploit their intrinsic charge transport properties for advanced electronics.