Challenges and Opportunities for RISC-V Architectures towards Genomics-based Workloads

TL;DR

This paper evaluates the potential of RISC-V architectures for genomics workloads, specifically using a benchmarking suite for Variant-Interaction Analytics, comparing performance with x86 supercomputers, and discussing future RISC-V developments.

Contribution

It introduces a genomics benchmarking suite for RISC-V, compares RISC-V and x86 architectures on real workloads, and discusses challenges and opportunities for RISC-V in scientific computing.

Findings

RISC-V shows promise for genomics workloads.

Performance comparison highlights current gaps and potential improvements.

Identifies key challenges for RISC-V adoption in high-performance computing.

Abstract

The use of large-scale supercomputing architectures is a hard requirement for scientific computing Big-Data applications. An example is genomics analytics, where millions of data transformations and tests per patient need to be done to find relevant clinical indicators. Therefore, to ensure open and broad access to high-performance technologies, governments, and academia are pushing toward the introduction of novel computing architectures in large-scale scientific environments. This is the case of RISC-V, an open-source and royalty-free instruction-set architecture. To evaluate such technologies, here we present the Variant-Interaction Analytics use case benchmarking suite and datasets. Through this use case, we search for possible genetic interactions using computational and statistical methods, providing a representative case for heavy ETL (Extract, Transform, Load) data processing. Current implementations are implemented in x86-based supercomputers (e.g. MareNostrum-IV at the Barcelona Supercomputing Center (BSC)), and future steps propose RISC-V as part of the next MareNostrum generations. Here we describe the Variant Interaction Use Case, highlighting the characteristics leveraging high-performance computing, indicating the caveats and challenges towards the next RISC-V developments and designs to come from a first comparison between x86 and RISC-V architectures on real Variant Interaction executions over real hardware implementations.