C3S Micro-architectural Enhancement: Spike Encoder Block and Relaxing Gamma Clock (Asynchronous)

TL;DR

This paper introduces a binary-to-spike encoder and a relaxed Gamma cycle controller to enhance neuromorphic cortical architectures, aiming to improve efficiency and biological plausibility in temporal neural networks.

Contribution

It presents novel designs for a binary-to-spike encoder and an adaptive Gamma cycle controller, addressing key challenges in neuromorphic computing architectures.

Findings

The encoder effectively translates binary data into timed spikes.

The Gamma cycle relaxation reduces processing idleness.

Enhanced system performance and efficiency demonstrated.

Abstract

The field of neuromorphic computing is rapidly evolving. As both biological accuracy and practical implementations are explored, existing architectures are modified and improved for both purposes. The Temporal Neural Network(TNN) style of architecture is a good basis for approximating biological neurons due to its use of timed pulses to encode data and a voltage-threshold-like system. Using the Temporal Neural Network cortical column C3S architecture design as a basis, this project seeks to augment the network's design. This project takes note of two ideas and presents their designs with the goal of improving existing cortical column architecture. One need in this field is for an encoder that could convert between common digital formats and timed neuronal spikes, as biologically accurate networks are temporal in nature. To this end, this project presents an encoder to translate between binary encoded values and timed spikes to be processed by the neural network. Another need is for the reduction of wasted processing time to idleness, caused by lengthy Gamma cycle processing bursts. To this end, this project presents a relaxation of Gamma cycles to allow for them to end arbitrarily early once the network has determined an output response. With the goal of contributing to the betterment of the field of neuromorphic computer architecture, designs for both a binary-to-spike encoder, as well as a Gamma cycle controller, are presented and evaluated for optimal design parameters, with overall system gain and performance.