Efficient and Scalable MIV-transistor with Extended Gate in Monolithic 3D Integration

TL;DR

This paper presents a novel MIV-transistor design for monolithic 3D integration that significantly reduces leakage and improves performance metrics while maintaining minimal area overhead, enabling more efficient future computing architectures.

Contribution

The work introduces an MIV-transistor that addresses leakage and scaling issues, achieving substantial improvements over previous designs in leakage current, maximum current, and circuit performance.

Findings

Leakage current reduced by 14,000 times

Maximum current increased by 58%

Inverter delay reduced by 11.6%

Abstract

Monolithic 3D integration has become a promising solution for future computing needs. The metal inter-layer via (MIV) forms interconnects between substrate layers in Monolithic 3D integration. Despite small size of MIV, the area overhead can become a major limitation for efficient M3D integration and, thus needs to be addressed. Previous works focused on the utilization of the substrate area around MIV to reduce this area overhead significantly but suffers from increased leakage and scaling factors. In this work, we discuss MIV-transistor realization that addresses both leakage and scaling issue along with similar area overhead reduction compared with previous works and, thus can be utilized efficiently. Our simulation results suggest that the leakage current $(I_{D,leak})$ has reduced by $14K\times$ and, the maximum current $(I_{D,max})$ increased by $58\%$ for the proposed MIV-transistor compared with the previous implementation. In addition, performance metrics of the inverter realization with our proposed MIV-transistor specifically the delay, slew time and power consumption reduced by $11.6\%$, $17.9\%$ and, $4.5\%$ respectively compared with the previous implementation with same MIV area overhead reduction.