FDSOI Process Based MIV-transistor Utilization for Standard Cell Designs in Monolithic 3D Integration

TL;DR

This paper explores the use of MIV-transistors in FDSOI-based monolithic 3D ICs to reduce layout area and improve power and delay metrics through a novel utilization strategy and standard cell comparison.

Contribution

It introduces a new method for utilizing MIVs as transistors in monolithic 3D integration, along with a parameter extraction strategy and a comparative PPA analysis.

Findings

Achieved 18% reduction in layout area on average.

Reduced power consumption by 1%.

Lowered delay time by 3%.

Abstract

Monolithic Three-Dimensional Integrated Circuits (M3D-IC) has become an attractive option to increase the transistor density. In M3D-IC, substrate layers are realized on top of previous layers using sequential integration techniques. Recent works in M3D-IC have demonstrated the feasibility of FDSOI process-based M3D-IC implementations and, Metal inter-layer vias (MIVs) are used to provide connections between the inter-layer devices. Since MIVs are extended from bottom layer to top layer, they occupy a small area resulting in area overhead. Additionally, a minimum separation is required to facilitate connection between MIV and transistors which increases this overhead further. Towards this, we studied the alternate utilization of MIV to create MIV-transistors with varying channels. We have also presented a strategy to extract the Spice parameters of the proposed models using level 70 spice parameters. Finally, a standard cell based gate level comparison is presented to compare the Power, Performance and Area (PPA) metrics of the traditional two layer 2D FDSOI transistor implementation with the proposed models. Simulation results from standard cell designs suggest that the proposed methodology can reduce 18\% layout area on average compared to the traditional approach. In addition, power consumption and delay time of the standard cells are reduced by 1\% and 3\% on average respectively.