An Introduction to the Compute Express Link (CXL) Interconnect

TL;DR

The paper introduces the Compute Express Link (CXL) standard, detailing its evolution, implementations, and impact on datacenter architectures, emphasizing its role in enabling high-performance, coherent interconnects for diverse computing devices.

Contribution

It provides a comprehensive survey of CXL standards, implementations, and its influence on datacenter design, highlighting future directions and industry adoption.

Findings

CXL offers high-bandwidth, low-latency coherent interconnects.

Major industry players have adopted CXL as a standard.

CXL enables new data center architectures and resource sharing.

Abstract

The Compute Express Link (CXL) is an open industry-standard interconnect between processors and devices such as accelerators, memory buffers, smart network interfaces, persistent memory, and solid-state drives. CXL offers coherency and memory semantics with bandwidth that scales with PCIe bandwidth while achieving significantly lower latency than PCIe. All major CPU vendors, device vendors, and datacenter operators have adopted CXL as a common standard. This enables an inter-operable ecosystem that supports key computing use cases including highly efficient accelerators, server memory bandwidth and capacity expansion, multi-server resource pooling and sharing, and efficient peer-to-peer communication. This survey provides an introduction to CXL covering the standards CXL 1.0, CXL 2.0, and CXL 3.0. We further survey CXL implementations, discuss CXL's impact on the datacenter landscape, and future directions.