Accelerating 128-bit Floating-Point Matrix Multiplication on FPGAs

TL;DR

This paper presents a high-performance FPGA implementation of 128-bit floating-point matrix multiplication, significantly accelerating scientific computations like semidefinite programming and LU decomposition compared to CPU solutions.

Contribution

It introduces a novel FPGA-based binary128 GEMM design that achieves high throughput and enables acceleration of complex numerical applications previously limited by hardware support.

Findings

Achieved approximately 90 GFlops on FPGA for binary128 GEMM.

Delivered 147x speedup over 20-thread CPU for large matrices.

First FPGA acceleration of LU decomposition and SDP problems using binary128 arithmetic.

Abstract

General Matrix Multiplication (GEMM) is a fundamental operation widely used in scientific computations. Its performance and accuracy significantly impact the performance and accuracy of applications that depend on it. One such application is semidefinite programming (SDP), and it often requires binary128 or higher precision arithmetic to solve problems involving SDP stably. However, only some processors support binary128 arithmetic, which makes SDP solvers generally slow. In this study, we focused on accelerating GEMM with binary128 arithmetic on field-programmable gate arrays (FPGAs) to enable the flexible design of accelerators for the desired computations. Our binary128 GEMM designs on a recent high-performance FPGA achieved approximately 90GFlops, 147x faster than the computation executed on a recent CPU with 20 threads for large matrices. Using our binary128 GEMM design on the FPGA, we successfully accelerated two numerical applications: LU decomposition and SDP problems, for the first time.