A Novel Implementation Methodology for Error Correction Codes on a Neuromorphic Architecture

TL;DR

This paper introduces a new methodology for implementing error correction decoders on neuromorphic architectures, demonstrating energy efficiency improvements while maintaining performance.

Contribution

It is the first to map hard-decision ECC decoders onto neuromorphic hardware, specifically implementing Gallager B decoding on a TrueNorth-inspired system.

Findings

Energy consumption reduced by 31%

Same error correction performance achieved

Architectural modifications are resource-efficient

Abstract

The Internet of Things infrastructure connects a massive number of edge devices with an increasing demand for intelligent sensing and inferencing capability. Such data-sensitive functions necessitate energy-efficient and programmable implementations of Error Correction Codes (ECC) and decoders. The algorithmic flow of ECCs with concurrent accumulation and comparison types of operations are innately exploitable by neuromorphic architectures for energy efficient execution -- an area that is relatively unexplored outside of machine learning applications. For the first time, we propose a methodology to map the hard-decision class of decoder algorithms on a neuromorphic architecture. We present the implementation of the Gallager B (GaB) decoding algorithm on a TrueNorth-inspired architecture that is emulated on the Xilinx Zynq ZCU102 MPSoC. Over this reference implementation, we propose architectural modifications at the neuron block level that result in a reduction of energy consumption by 31% with a negligible increase in resource usage while achieving the same error correction performance.