FPIM: Field-Programmable Ising Machines for Solving SAT

TL;DR

This paper introduces FPIM, a reconfigurable analog Ising machine designed for solving SAT problems efficiently on-chip, demonstrating scalability, low resource requirements, and suitability for various problem topologies.

Contribution

The paper presents FPIM, a novel on-chip analog Ising machine architecture optimized for SAT, with scalable mapping, low sparsity, and low coupling resolution requirements.

Findings

Successfully mapped 2000 SAT benchmarks onto FPIM

Achieved low sparsity and BCR independent of problem size

Required less than 10 routing tracks, about 10mm^2 chip area

Abstract

On-chip analog Ising Machines (IMs) are a promising means to solve difficult combinatorial optimization problems. For scalable on-chip realizations to be practical, 1) the problem should map scalably to Ising form, 2) interconnectivity between spins should be sparse, 3) the number of bits of coupling resolution (BCR) needed for programming interconnection weights should be small, and 4) the chip should be capable of solving problems with different connection topologies. We explore these issues for the SATisfiability problem and devise FPIM, a reconfigurable on-chip analog Ising machine scheme well suited for SAT. To map SAT problems onto FPIMs, we leverage Boolean logic synthesis as a first step, but replace synthesized logic gates with Ising equivalent circuits whose analog dynamics solve SAT by minimizing the Ising Hamiltonian. We apply our approach to 2000 benchmark problems from SATLIB,demonstrating excellent scaling, together with low sparsity and low BCR that are independent of problem scale. Placement/routing reveals a very feasible requirement of less than 10 routing tracks to implement all the benchmarks, translating to an area requirement of about 10mm^2 for a programmable 1000-spin FPIM in 65nm technology.