A 3-step Low-latency Low-Power Multichannel Time-to-Digital Converter based on Time Residual Amplifier
Florent Bouyjou

TL;DR
This paper introduces a three-step low-power, high-resolution multichannel Time-to-Digital Converter (TDC) architecture optimized for integration and high-rate operation, achieving 24.4 ps resolution with minimal power and area.
Contribution
A novel three-step TDC architecture with integrated calibration and low power consumption suitable for multi-channel chips.
Findings
Achieved 24.4 ps resolution in prototype
Power consumption limited to 2.2 mW per channel during operation
Timing precision better than 21 ps RMS
Abstract
This paper proposes and evaluates a novel architecture for a low-power Time-to-Digital Converter with high resolution, optimized for both integration in multichannel chips and high rate operation (40 Mconversion/s/channel). This converter is based on a three-step architecture. The first step uses a counter whereas the following ones are based on two kinds of Delay Line structures. A programmable time amplifier is used between the second and third steps to reach the final resolution of 24.4 ps in the standard mode of operation. The system makes use of common continuously stabilized master blocks that control trimmable slave blocks, in each channel, against the effects of global PVT variations. Thanks to this structure, the power consumption of a channel is considerably reduced when it does not process a hit, and limited to 2.2 mW when it processes a hit. In the 130 nm CMOS technology…
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Taxonomy
TopicsAdvancements in PLL and VCO Technologies · Semiconductor materials and devices · Analog and Mixed-Signal Circuit Design
MethodsMulti-Head Attention · Attention Is All You Need · Linear Layer · Softmax · Spatial-Reduction Attention · Residual Connection · Layer Normalization · Absolute Position Encodings · Dense Connections · Pyramid Vision Transformer
