Robust Power Allocation for Integrated Visible Light Positioning and Communication Networks

TL;DR

This paper presents a robust power allocation scheme for integrated visible light positioning and communication networks, optimizing positioning accuracy and data rate under uncertainty using advanced convex optimization techniques.

Contribution

It introduces a novel approach that explicitly models positioning and channel errors, transforming complex chance constraints into tractable convex problems for the first time.

Findings

The proposed scheme improves robustness against positioning errors.

Simulation confirms enhanced positioning and communication performance.

The method effectively handles arbitrary error distributions.

Abstract

Integrated visible light positioning and communication (VLPC), capable of combining advantages of visible light communications (VLC) and visible light positioning (VLP), is a promising key technology for the future Internet of Things. In VLPC networks, positioning and communications are inherently coupled, which has not been sufficiently explored in the literature. We propose a robust power allocation scheme for integrated VLPC Networks by exploiting the intrinsic relationship between positioning and communications. Specifically, we derive explicit relationships between random positioning errors, following both a Gaussian distribution and an arbitrary distribution, and channel state information errors. Then, we minimize the Cramer-Rao lower bound (CRLB) of positioning errors, subject to the rate outage constraint and the power constraints, which is a chance-constrained optimization problem and generally computationally intractable. To circumvent the nonconvex challenge, we conservatively transform the chance constraints to deterministic forms by using the Bernstein-type inequality and the conditional value-at-risk for the Gaussian and arbitrary distributed positioning errors, respectively, and then approximate them as convex semidefinite programs. Finally, simulation results verify the robustness and effectiveness of our proposed integrated VLPC design schemes.