Case Study for Running Memory-Bound Kernels on RISC-V CPUs

TL;DR

This study evaluates RISC-V CPUs' performance on memory-bound applications, highlighting their resource efficiency and potential for high-performance computing despite current computational limitations.

Contribution

It provides a comprehensive performance analysis of RISC-V devices on memory-bound workloads and explores the effectiveness of memory optimization techniques.

Findings

RISC-V devices are resource-efficient compared to x86 and ARM.

Memory optimization techniques improve RISC-V performance.

RISC-V shows potential for high-performance computing applications.

Abstract

The emergence of a new, open, and free instruction set architecture, RISC-V, has heralded a new era in microprocessor architectures. Starting with low-power, low-performance prototypes, the RISC-V community has a good chance of moving towards fully functional high-end microprocessors suitable for high-performance computing. Achieving progress in this direction requires comprehensive development of the software environment, namely operating systems, compilers, mathematical libraries, and approaches to performance analysis and optimization. In this paper, we analyze the performance of two available RISC-V devices when executing three memory-bound applications: a widely used STREAM benchmark, an in-place dense matrix transposition algorithm, and a Gaussian Blur algorithm. We show that, compared to x86 and ARM CPUs, RISC-V devices are still expected to be inferior in terms of computation time but are very good in resource utilization. We also demonstrate that well-developed memory optimization techniques for x86 CPUs improve the performance on RISC-V CPUs. Overall, the paper shows the potential of RISC-V as an alternative architecture for high-performance computing.