Hardware Acceleration of Explainable Artificial Intelligence
Zhixin Pan, Prabhat Mishra

TL;DR
This paper introduces a novel TPU-based hardware acceleration framework for explainable AI algorithms, enabling real-time interpretation with significant improvements in speed and energy efficiency.
Contribution
It is the first to explore TPU acceleration for XAI, leveraging matrix computation synergy to enhance interpretability speed and efficiency.
Findings
39x faster interpretation time on average
69x better energy efficiency
Effective acceleration of various XAI algorithms
Abstract
Machine learning (ML) is successful in achieving human-level artificial intelligence in various fields. However, it lacks the ability to explain an outcome due to its black-box nature. While recent efforts on explainable AI (XAI) has received significant attention, most of the existing solutions are not applicable in real-time systems since they map interpretability as an optimization problem, which leads to numerous iterations of time-consuming complex computations. Although there are existing hardware-based acceleration framework for XAI, they are implemented through FPGA and designed for specific tasks, leading to expensive cost and lack of flexibility. In this paper, we propose a simple yet efficient framework to accelerate various XAI algorithms with existing hardware accelerators. Specifically, this paper makes three important contributions. (1) The proposed method is the first…
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Taxonomy
TopicsParallel Computing and Optimization Techniques · Advanced Neural Network Applications · Tensor decomposition and applications
MethodsConvolution
