BackCache: Mitigating Contention-Based Cache Timing Attacks by Hiding Cache Line Evictions
Quancheng Wang, Xige Zhang, Han Wang, Yuzhe Gu, Ming Tang

TL;DR
BackCache is a hardware-software co-design that mitigates cache timing attacks by ensuring cache hits through a backup cache system, with minimal performance overhead demonstrated in simulation.
Contribution
It introduces a novel cache architecture with a backup cache and dynamic policies to prevent cache eviction side channels, enhancing security against contention-based attacks.
Findings
Degrades performance by less than 3.36% in benchmarks.
Effectively hides cache evictions to prevent timing attacks.
Theoretical security analysis confirms robustness.
Abstract
Caches are used to reduce the speed differential between the CPU and memory to improve the performance of modern processors. However, attackers can use contention-based cache timing attacks to steal sensitive information from victim processes through carefully designed cache eviction sets. And L1 data cache attacks are widely exploited and pose a significant privacy and confidentiality threat. Existing hardware-based countermeasures mainly focus on cache partitioning, randomization, and cache line flushing, which unfortunately either incur high overhead or can be circumvented by sophisticated attacks. In this paper, we propose a novel hardware-software co-design called BackCache with the idea of always achieving cache hits instead of cache misses to mitigate contention-based cache timing attacks on the L1 data cache. BackCache places the evicted cache lines from the L1 data cache into a…
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Taxonomy
TopicsSecurity and Verification in Computing · Cloud Data Security Solutions · Parallel Computing and Optimization Techniques
