Fault Tolerant FPGA Implementation on Redundancy Techniques and ECG Denoising

TL;DR

This paper presents a fault-tolerant FPGA implementation using 5-modular redundancy techniques to improve reliability in digital signal processing, specifically for ECG denoising with FIR filters.

Contribution

It introduces a novel FPGA design employing 5-modular redundancy for fault tolerance in ECG signal denoising using FIR filters.

Findings

Reduced error rates in FPGA-based ECG denoising

Enhanced reliability of digital signal processing systems

Effective noise reduction in ECG signals

Abstract

As more the communications and signal process we use in the today life the more we intend to develop more reliable devices which gives fewer errors due to transient fault, So we use a technique called 5-modular redundancy to generate fewer errors. 5-Modular redundancy is an approach to increasing the reliability of hardware systems constructed from component devices that are subject to failure. In digital signal processing and many other important daily life subjects FIR digital filters are used and they alike performing multiplications, complex computations and selecting desired frequency for different applications. FIR filters comprise of multipliers, adders, delay units. FIR filters has been chosen because it offers more steadiness and simple execution because of its limited length and no feedback within the circuit. Fir filter is most important for the signal processing and also used in daily life basis. The noise reduction can be performed by denoising of the signals of all the implementations .The proposed FPGA methods use Xilinx Vivado EDA.