Compact and High-Performance TCAM Based on Scaled Double-Gate FeFETs

TL;DR

This paper presents a novel 1.5T1Fe DG-FeFET-based TCAM design that enhances search speed and energy efficiency, addressing scaling and endurance issues of conventional FeFETs for high-performance memory applications.

Contribution

It introduces a new 1.5T1Fe TCAM architecture using double-gate FeFETs with a 2-step search method, improving speed and energy efficiency over existing designs.

Findings

1.5T1Fe DG-TCAM achieves faster search speeds.

Significant energy efficiency improvements demonstrated.

Design adaptable to single-gate FeFETs for better performance.

Abstract

Ternary content addressable memory (TCAM), widely used in network routers and high-associativity caches, is gaining popularity in machine learning and data-analytic applications. Ferroelectric FETs (FeFETs) are a promising candidate for implementing TCAM owing to their high ON/OFF ratio, non-volatility, and CMOS compatibility. However, conventional single-gate FeFETs (SG-FeFETs) suffer from relatively high write voltage, low endurance, potential read disturbance, and face scaling challenges. Recently, a double-gate FeFET (DG-FeFET) has been proposed and outperforms SG-FeFETs in many aspects. This paper investigates TCAM design challenges specific to DG-FeFETs and introduces a novel 1.5T1Fe TCAM design based on DG-FeFETs. A 2-step search with early termination is employed to reduce the cell area and improve energy efficiency. A shared driver design is proposed to reduce the peripherals area. Detailed analysis and SPICE simulation show that the 1.5T1Fe DG-TCAM leads to superior search speed and energy efficiency. The 1.5T1Fe TCAM design can also be built with SG-FeFETs, which achieve search latency and energy improvement compared with 2FeFET TCAM.