The Error Reconstruction and Compiled Calibration of Quantum Computing Cycles

TL;DR

This paper introduces cycle error reconstruction (CER) and stochastic calibration (SC) techniques to improve error characterization and suppression in quantum computing, demonstrating significant performance gains on IBM-Q devices.

Contribution

The paper presents novel scalable methods for error profile estimation and calibration of quantum cycles, enhancing error suppression in quantum processors.

Findings

CER accurately estimates cycle error distributions with multiplicative precision.

SC achieves up to 5-fold improvement in circuit performance.

Methods are validated on IBM-Q 5-qubit devices.

Abstract

Quantum computers are inhibited by physical errors that occur during computation. For this reason, the development of increasingly sophisticated error characterization and error suppression techniques is central to the progress of quantum computing. Error distributions are considerably influenced by the precise gate scheduling across the entire quantum processing unit. To account for this holistic feature, we may ascribe each error profile to a (clock) cycle, which is a scheduled list of instructions over an arbitrarily large fraction of the chip. A celebrated technique known as randomized compiling introduces some randomness within cycles' instructions, which yields effective cycles with simpler, stochastic error profiles. In the present work, we leverage the structure of cycle benchmarking (CB) circuits as well as known Pauli channel estimation techniques to derive a method, which we refer to as cycle error reconstruction (CER), to estimate with multiplicative precision the marginal error distribution associated with any effective cycle of interest. The CER protocol is designed to scale for an arbitrarily large number of qubits. Furthermore, we develop a fast compilation-based calibration method, referred to as stochastic calibration (SC), to identify and suppress local coherent error sources occurring in any effective cycle of interest. We performed both protocols on IBM-Q 5-qubit devices. Via our calibration scheme, we obtained up to a 5-fold improvement of the circuit performance.