A Cycle-level Unified DRAM Cache Controller Model for 3DXPoint Memory Systems in gem5

TL;DR

This paper introduces a cycle-level DRAM cache model integrated with gem5, enabling detailed exploration of DRAM cache designs and their impact on system performance with various memory technologies and workloads.

Contribution

The work presents a novel, flexible DRAM cache model for gem5 that supports diverse memory technologies and enables comprehensive design space exploration.

Findings

DRAM cache size significantly affects workload performance

Scheduling policies impact cache efficiency

Wear-leveling influences cache longevity

Abstract

To accommodate the growing memory footprints of today's applications, CPU vendors have employed large DRAM caches, backed by large non-volatile memories like Intel Optane (e.g., Intel's Cascade Lake). The existing computer architecture simulators do not provide support to model and evaluate systems which use DRAM devices as a cache to the non-volatile main memory. In this work, we present a cycle-level DRAM cache model which is integrated with gem5. This model leverages the flexibility of gem5's memory devices models and full system support to enable exploration of many different DRAM cache designs. We demonstrate the usefulness of this new tool by exploring the design space of a DRAM cache controller through several case studies including the impact of scheduling policies, required buffering, combining different memory technologies (e.g., HBM, DDR3/4/5, 3DXPoint, High latency) as the cache and main memory, and the effect of wear-leveling when DRAM cache is backed by NVM main memory. We also perform experiments with real workloads in full-system simulations to validate the proposed model and show the sensitivity of these workloads to the DRAM cache sizes.