A High-Performance Accelerator for Super-Resolution Processing on Embedded GPU

TL;DR

This paper presents a full-stack acceleration framework for super-resolution on embedded GPUs, combining novel algorithms and hardware optimization to achieve real-time inference performance.

Contribution

It introduces a dictionary selective strategy and an optimized hardware architecture for efficient SR processing on embedded GPUs, addressing latency and resource constraints.

Findings

Outperforms state-of-the-art NVIDIA TensorRT in SR tasks

Achieves real-time super-resolution on embedded NVIDIA devices

Effectively reduces communication and computation bottlenecks

Abstract

Recent years have witnessed impressive progress in super-resolution (SR) processing. However, its real-time inference requirement sets a challenge not only for the model design but also for the on-chip implementation. In this paper, we implement a full-stack SR acceleration framework on embedded GPU devices. The special dictionary learning algorithm used in SR models was analyzed in detail and accelerated via a novel dictionary selective strategy. Besides, the hardware programming architecture together with the model structure is analyzed to guide the optimal design of computation kernels to minimize the inference latency under the resource constraints. With these novel techniques, the communication and computation bottlenecks in the deep dictionary learning-based SR models are tackled perfectly. The experiments on the edge embedded NVIDIA NX and 2080Ti show that our method outperforms the state-of-the-art NVIDIA TensorRT significantly, and can achieve real-time performance.