Word-Level Structure Identification In FPGA Designs Using Cell Proximity Information

TL;DR

This paper introduces a method for reverse engineering FPGA netlists by leveraging cell proximity information to identify structure and group design elements, aiding in design understanding and verification.

Contribution

It presents a novel cell grouping algorithm that uses physical location data to improve reverse engineering of FPGA designs from flattened netlists.

Findings

Achieved an average NMI of 0.73 in clustering accuracy

Effective across diverse FPGA design types

Facilitates high-level understanding of FPGA layouts

Abstract

Reverse engineering of FPGA based designs from the flattened LUT level netlist to high level RTL helps in verification of the design or in understanding legacy designs. We focus on flattened netlists for FPGA devices from Xilinx 7 series and Zynq 7000. We propose a design element grouping algorithm that makes use of the location information of the elements on the physical device after place and route. The proposed grouping algorithm gives clusters with average NMI of 0.73 for groupings including all element types. The benchmarks chosen include a range of designs from communication, arithmetic units, processors and DSP processing units.