Hierarchical memories: Simulating quantum LDPC codes with local gates

TL;DR

This paper introduces hierarchical quantum LDPC codes that combine LDPC and surface codes, enabling local gate implementation with superpolynomial error suppression, advancing fault-tolerant quantum memory design.

Contribution

The paper constructs a new family of hierarchical quantum codes that encode many logical qubits using local gates, combining LDPC and surface codes for improved fault tolerance.

Findings

Hierarchical codes encode   times more logical qubits than surface codes.

Superpolynomial decay of logical failure rate below threshold.

Hierarchical codes outperform basic surface code encoding under conservative assumptions.

Abstract

Constant-rate low-density parity-check (LDPC) codes are promising candidates for constructing efficient fault-tolerant quantum memories. However, if physical gates are subject to geometric-locality constraints, it becomes challenging to realize these codes. In this paper, we construct a new family of $[[N,K,D]]$ codes, referred to as hierarchical codes, that encode a number of logical qubits $K = \Omega(N/\log(N)^2)$. The N-th element of this code family is obtained by concatenating a constant-rate quantum LDPC code with a surface code; nearest-neighbor gates in two dimensions are sufficient to implement the corresponding syndrome-extraction circuit and achieve a threshold. Below threshold the logical failure rate vanishes superpolynomially as a function of the distance $D(N)$. We present a bilayer architecture for implementing the syndrome-extraction circuit, and estimate the logical failure rate for this architecture. Under conservative assumptions, we find that the hierarchical code outperforms the basic encoding where all logical qubits are encoded in the surface code.