Xel-FPGAs: An End-to-End Automated Exploration Framework for Approximate Accelerators in FPGA-Based Systems

TL;DR

Xel-FPGAs is an automated framework that adapts ASIC-based approximate circuits for FPGA accelerators, significantly reducing exploration time and improving design quality using machine learning models.

Contribution

The paper introduces Xel-FPGAs, a novel framework that leverages machine learning to efficiently explore and adapt ASIC-based approximate circuits for FPGA systems.

Findings

Reduces exploration time by up to 95%

Identifies Pareto-optimal designs more effectively

Scalable to multi-stage applications

Abstract

Generation and exploration of approximate circuits and accelerators has been a prominent research domain to achieve energy-efficiency and/or performance improvements. This research has predominantly focused on ASICs, while not achieving similar gains when deployed for FPGA-based accelerator systems, due to the inherent architectural differences between the two. In this work, we propose a novel framework, Xel-FPGAs, which leverages statistical or machine learning models to effectively explore the architecture-space of state-of-the-art ASIC-based approximate circuits to cater them for FPGA-based systems given a simple RTL description of the target application. We have also evaluated the scalability of our framework on a multi-stage application using a hierarchical search strategy. The Xel-FPGAs framework is capable of reducing the exploration time by up to 95%, when compared to the default synthesis, place, and route approaches, while identifying an improved set of Pareto-optimal designs for a given application, when compared to the state-of-the-art. The complete framework is open-source and available online at https://github.com/ehw-fit/xel-fpgas.