Automating Constraint-Aware Datapath Optimization using E-Graphs

TL;DR

This paper presents an automated RTL optimization tool that leverages abstract interpretation and e-graphs to exploit branch constraints, leading to significant improvements in circuit speed and size.

Contribution

It introduces a novel method combining abstract interpretation with e-graphs for constraint-aware hardware optimization, outperforming existing EDA tools.

Findings

Achieves up to 33% faster circuits

Reduces circuit size by up to 41%

Successfully automates discovery of floating-point architectures

Abstract

Numerical hardware design requires aggressive optimization, where designers exploit branch constraints, creating optimization opportunities that are valid only on a sub-domain of input space. We developed an RTL optimization tool that automatically learns the consequences of conditional branches and exploits that knowledge to enable deep optimization. The tool deploys custom built program analysis based on abstract interpretation theory, which when combined with a data-structure known as an e-graph simplifies complex reasoning about program properties. Our tool fully-automatically discovers known floating-point architectures from the computer arithmetic literature and out-performs baseline EDA tools, generating up to 33% faster and 41% smaller circuits.