Co-Design of Approximate Multilayer Perceptron for Ultra-Resource Constrained Printed Circuits

TL;DR

This paper introduces a co-design framework for approximate printed multilayer perceptrons that significantly reduces area and power consumption while maintaining high accuracy, enabling ML applications on ultra-resource constrained printed electronics.

Contribution

It presents the first automated printed-aware co-design framework for approximate ML circuits tailored for printed electronics, achieving substantial resource savings.

Findings

6x reduction in circuit area

5.7x reduction in power consumption

Less than 1% accuracy loss

Abstract

Printed Electronics (PE) exhibits on-demand, extremely low-cost hardware due to its additive manufacturing process, enabling machine learning (ML) applications for domains that feature ultra-low cost, conformity, and non-toxicity requirements that silicon-based systems cannot deliver. Nevertheless, large feature sizes in PE prohibit the realization of complex printed ML circuits. In this work, we present, for the first time, an automated printed-aware software/hardware co-design framework that exploits approximate computing principles to enable ultra-resource constrained printed multilayer perceptrons (MLPs). Our evaluation demonstrates that, compared to the state-of-the-art baseline, our circuits feature on average 6x (5.7x) lower area (power) and less than 1% accuracy loss.