# Intel Stratix 10 FPGA design for track reconstruction for the ATLAS experiment at the HL-LHC

## TL;DR

This paper presents the FPGA design for the Pattern Recognition Mezzanine (PRM) in the ATLAS experiment's Hardware Tracking Trigger system, demonstrating its functionality through simulations and hardware tests to enable fast, efficient track reconstruction at the HL-LHC.

## Contribution

It introduces a novel FPGA-based design for the PRM board utilizing Intel Stratix 10 MX FPGA and High-Bandwidth-Memory for real-time track recognition in high-energy physics experiments.

## Key findings

- Design verified through simulations
- Hardware tests confirm functionality
- Efficient track recognition demonstrated

## Abstract

The fast reconstruction of charged particle tracks with high efficiency and track quality is an essential part of the online data selection for the ATLAS experiment at the High-Luminosity LHC. Dedicated custom designed hardware boards and software simulations have been developed to assess the feasibility of a Hardware Tracking Trigger (HTT) system. The Pattern Recognition Mezzanine (PRM), as part of the HTT system, has been designed to recognize track candidates in silicon detectors with Associative Memory ASICs and to select and reconstruct tracks using linearized algorithms implemented in an Intel Stratix 10 MX FPGA. The highly parallelized FPGA design makes extensive use of the integrated High-Bandwidth-Memory. In this paper, the FPGA design for the PRM board is presented. Its functionalities have been verified in both simulations and hardware tests on an Intel Stratix 10 MX development kit.