A Bit-Parallel Deterministic Stochastic Multiplier

TL;DR

This paper introduces a new bit-parallel deterministic stochastic multiplier that significantly enhances efficiency and accuracy over previous designs, achieving up to 10.6×10^4 improvements in area-energy-latency and reducing error by 32.2%.

Contribution

It proposes a novel multiplier architecture that outperforms prior stochastic multipliers in efficiency and accuracy.

Findings

Up to 10.6×10^4 improvement in area-energy-latency product.

32.2% reduction in computational error.

Superior performance compared to three prior stochastic multipliers.

Abstract

This paper presents a novel bit-parallel deterministic stochastic multiplier, which improves the area-energy-latency product by up to 10.6$\times$10$^4$, while improving the computational error by 32.2\%, compared to three prior stochastic multipliers.