An Implementation of a Dual-Processor System on FPGA

TL;DR

This paper presents the design and implementation of a dual-processor system on FPGA, optimizing resource utilization and evaluating performance against industry-standard CPUs.

Contribution

It introduces a tightly-coupled FPGA-based dual-processor platform with practical cache design considerations and performance evaluation.

Findings

Dual-processor FPGA system improves processing capabilities.

Performance comparisons show advantages over uniprocessor configurations.

Resource optimization enhances FPGA utilization.

Abstract

In recent years, Field-Programmable Gate Arrays (FPGA) have evolved rapidly paving the way for a whole new range of computing paradigms. On the other hand, computer applications are evolving. There is a rising demand for a system that is general-purpose and yet has the processing abilities to accommodate current trends in application processing. This work proposes a design and implementation of a tightly-coupled FPGA-based dual-processor platform. We architect a platform that optimizes the utilization of FPGA resources and allows for the investigation of practical implementation issues such as cache design. The performance of the proposed prototype is then evaluated, as different configurations of a uniprocessor and a dual-processor system are studied and compared against each other and against published results for common industry-standard CPU platforms. The proposed implementation utilizes the Nios II 32-bit embedded soft-core processor architecture designed for the Altera Cyclone III family of FPGAs.